Image smoothing and edge detection CMOS sensor array with improved signal output range

摘要

This paper consists of design, simulation, layout, and test of a CMOS image sensor array. It is an analog nonlinear circuitry with on-board photoreceptors that acquire and process the image on a single, compact VLSI chip. Spatial image processing chips implementing resistive grid have been broadly explored. One of the main drawbacks of one group of these sensors is the large percentage of analog output signal loss due to the known low CMOS sensors sensitivity and the relative large offset of the readout amplifier caused by run-to-run and in chip process variations. In our design, we modified the pixel circuit and the read out transresistance amplifier gaining back close to fifty percent of the photo signal. The motivation of the overall chip is derived from its neurobiological counterpart. It models the first stage of retinal processing at the first synapse