Silent CMOS circuits aiming for system-on-chip

摘要

A silent CMOS circuit architecture is proposed. Different silent CMOS gate solutions are presented and compared to the normal CMOS precharged gate in switching noise level. A silent 16-bit parallel carry-look-ahead adder is demonstrated. Simulation results on the circuits and the post layout of the adder are given, which shows a 10 times reduction in noise level is possible.