The design verification for the 3DES encipher chip based on an extended Petri net and XML/Java executor

摘要

In this paper, we propose the new method for the parallel system design based on expanded the logical coloured Petri net (LCPN). An LCPN is an extended Petri net that solves the problem of system description in previously proposed place/transition nets and coloured Petri nets. This extension of Petri nets is suitable for designing complex control systems and for discussing methods of evaluating such systems realistically. In order to study the behaviour of the server system modelled with this net we simulated a Java program. This program confirmed that this extended Petri net is an effective tool for modelling the parallel system.