An all-digital clock generator firm-core based on differential fine-tuned delay for reusable microprocessor cores

摘要

Clock generator cores play an increasingly important role in the VLSI design of embedded microprocessors supporting specialized power management modes. We present a fully digital, standard-cell-based design of a specialized PLL architecture that can be recompiled on different cell libraries. On a 0.45 /spl mu/m CMOS implementation, the circuit features a 16 ps jitter, 19.5-to-72 MHz frequency range with a 32 KHz input, and less than 50 clock cycles wakeup time.