Low power and low voltage considerations in the design of a high frequency clock generator

摘要

A low voltage, 1.2 V, 4 GHZ CMOS phase lock loop for clock generation is reported. This low voltage clock generator consists of a ring oscillator as the VCO that works from 100 MHz to 4 GHZ with a maximum power consumption of 11 mW. Employing a charge pump circuit with suitable loop filter, a ripple free control voltage is provided for VCO. The total power consumption of this PLL, simulated in a 0.13 /spl mu/m CMOS technology, is about 54 mW.