The implementation of a new 3-D parallel filtering algorithm on the SHARC ADSP21060 platform

摘要

We present the implementation of a new parallel fast filtering algorithm for three-dimensional (3-D) applications on the SHARC DSP platform. The proposed 3-D algorithm eliminates the overhead associated with the overlapping segments in the block-filtering method, and the boundary conditions in parallel filtering implementation, as both the 3-D input and impulse response of the system are decimated by 2 prior to the filtering stage. Due to the nature of the input decimation process, this parallel algorithm solves the problem of limited efficiency in the block filtering when the impulse response is large, and enhances the overall memory distribution of the parallel system. Finally, the efficient implementation of the 3-D fast convolution algorithm on DSP hardware is presented using the 3-D new Mersenne number transform (3-D NMNT).