A low-power entropy-coding analog/digital converter with integrated data compression

摘要

A novel circuit architecture for integrated analog/digital converters (ADCs) is presented that allows exploiting the information-theoretic redundancy of the input signal for increasing the efficiency of operation. Analog/digital conversion and entropy-coding are combined in a single process such that integrated data compression as well as a low-power operation of the converter is obtained. A prototype ADC has been implemented in a 0.6 /spl mu/m CMOS process. Experimental results showing the performance of the converter as well as the achieved compression ratios and power savings are discussed.