Routing tools consume a significant portion of the total design time. Considering routability at earlier steps of the CAD flow would both yield better quality and faster design process. We present a routability-driven clustering method for cluster-based FPGAs. Our method packs LUTs into logic clusters while incorporating routability metrics into a cost function. The objective is to minimize this routability cost function. Our cost function is consistently able to indicate improved routability. Our method yields up to 50% improvement over existing clustering methods in terms of the number of routing tracks required. The average improvement obtained is 16.5%. Reduction in number of tracks yields reduced routing area.
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