A parameterised block-level layout generation system for CMOS analog ICs

摘要

This paper presents a full-custom building-block layout generation system that substantially improves the process of analog IC design automation. The tool generates layout for primitive devices and building blocks. Analog functional blocks are recognised by a set of knowledge rules and are extracted in a block-level netlist. The novel system architecture involves both "hard and "soft" sets of data in the generation phase, and achieves very significant savings in run time. The system's capability to improve analog layout quality is demonstrated through example results.