A VLSI implementation of a low-power DSP is described, which is dedicated to the G.723.1 low bitrate speech codec. A number of sophisticated DSP microarchitectures are devised mainly on dual multiply accumulators, rounding and saturation mechanisms, and two-banked on-chip memory. The proposed DSP architecture has been integrated in a total area of 7.75 mm/sup 2/ by using a 0.35 /spl mu/m CMOS technology, which can operate at 10 MHz with the dissipation of 45 mW from a single 3 V supply.
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机译：描述了一种低功耗DSP的VLSI实现，专用于G.723.1低比特率语音编解码器。许多复杂的DSP微体系结构主要设计在双乘法累加器，舍入和饱和机制以及两排片上存储器上。通过使用0.35 / spl mu / m CMOS技术，已将拟议的DSP体系结构集成到了7.75 mm / sup 2 /的总面积中，该技术可以在10 MHz的频率下工作，而3 V单电源的功耗为45 mW。
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