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0.5 /spl mu/m GaAs MESFET 4.2 mW ultra-low power decision circuit for optical communications with 0.1 /spl mu/m CMOS and HBT implementation

机译:0.5 / spl mu / m GaAs MESFET 4.2 mW超低功耗决策电路,用于采用0.1 / spl mu / m CMOS和HBT实现的光通信

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The design specifications considering low-power and high-speed are presented. Several decision circuits for an optical communication receiver system, are designed and simulated using AIM-SPICE circuit simulation tools, based on extracted process parameter using an in-house characterization and modeling tool named CMLEE. Several circuits using 2/spl times/4 emitter-area HBT, 0.5 /spl mu/m MESFET and compatible 0.1 /spl mu/m CMOS technology are designed and simulated for the output node waveform and power consumption. All the waveform simulations showed good performance at 10 Gbps. It is observed that the 0.1 /spl mu/m CMOS circuits of current mainstream electronic systems shows more than a 10 GHz operation, opening an opportunity for high frequency as long as deep sub-/spl mu/m technology compromises maturity and cost in reality. In terms of power consumption, the sub-half 0.5 /spl mu/m GaAs MESFET at 4.2 mW is the best choice for the same 10 GHz speed performance, compared to 60 mW by the 0.1 /spl mu/m CMOS circuit.
机译:提出了考虑低功耗和高速的设计规范。使用内部命名和建模工具CMLEE,基于提取的过程参数,使用AIM-SPICE电路仿真工具来设计和仿真光通信接收器系统的多个决策电路。针对输出节点波形和功耗,设计并仿真了使用2 / spl倍/ 4发射极面积HBT,0.5 / spl mu / m MESFET和兼容的0.1 / spl mu / m CMOS技术的电路。所有波形仿真均显示出10 Gbps时的良好性能。可以观察到,当前主流电子系统的0.1 / spl mu / m CMOS电路显示超过10 GHz的工作频率,只要深层sub // spl mu / m技术损害了成熟度和实际成本,就为高频提供了机会。 。就功耗而言,对于相同的10 GHz速度性能,在4.2 mW时,0.5 / spl mu / m的半个GaAs MESFET是最好的选择,而在0.1 / spl mu / m的CMOS电路中则为60 mW。

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