In this paper we present a new strategy of performance-directed technology mapping algorithm for LUT-based FPGAs to minimize both CLB levels on critical paths and total wire length. We first use a clustering approach to get a level-optimized mapping solution. Then we use a min-cut based block pairing algorithm to minimize the total wire length and the number of used CLBs. Experimental results on the MCNC benchmark circuits show that our algorithm is effective.
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