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Design of high performance sense amplifier using independent gate control in sub-50nm double-gate MOSFET

机译:低于50nm的双栅极MOSFET中采用独立栅极控制的高性能读出放大器设计

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摘要

The double-gate (DG) transistor has emerged as the most promising device for nanoscale circuit design. Independent control of front and back gate in DG devices can be effectively used to improve performance and reduce power in sub-50 nm circuits. In this paper, we propose a high-performance sense-amplifier design using independent gate control in symmetric and asymmetric DG devices. The proposed design reduces the sensing delay of the sense amplifier by 30-35% and dynamic power by 10% (at 6 GHz) from the connected gate design.
机译:双栅极(DG)晶体管已经成为纳米电路设计中最有前途的器件。 DG设备中前门和后门的独立控制可以有效地用于提高性能并降低50纳米以下电路的功耗。在本文中,我们提出了一种在对称和非对称DG设备中使用独立栅极控制的高性能读出放大器设计。与相连的门设计相比,拟议的设计将传感放大器的传感延迟降低了30-35%,动态功率降低了10%(在6 GHz时)。

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