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Adaptive Circuit Design Using Independently Biased Back-Gated Double-Gate MOSFETS

机译:使用独立偏置的后栅极双栅极MOSFET的自适应电路设计

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摘要

A new adaptive circuit design approach is proposed and analyzed employing independently biased back-gated Double-Gate MOSFET (DGMOSFET) devices. Threshold voltage tuning using back-gate of the DGMOSFET was compared with a conventional body-bias method. The technique is a promising solution to control the transistor's threshold voltage while reducing undesirable effects at the sub-50-nm device technology nodes. An automatic adaptive circuit for threshold voltage tuning was implemented using DGMOSFET devices in 45 nm CMOS technology. Simulation results show that this circuit compensates for static and dynamic variations. This adaptation approach using DGMOSFETs along with adaptive supply voltage scaling allows simultaneous optimization of power and performance according to application-specific workload and requirements. Simulation results using a 45 nm CMOS technology indicate that this adaptive circuit design can provide 50% higher performance for the same energy, or consume 40% less energy for the same performance. In contrast to conventional methods which only employ dynamic voltage scaling, adaptive tuning of threshold voltages reduces power consumption while maintaining its noise margin.
机译:提出并分析了一种新的自适应电路设计方法,该方法采用了独立偏置的背栅双栅极MOSFET(DGMOSFET)器件。将使用DGMOSFET的背栅进行阈值电压调整与常规的体偏置方法进行了比较。该技术是一种有前途的解决方案,它可以控制晶体管的阈值电压,同时减少在低于50 nm的器件技术节点上产生的不良影响。使用45 nm CMOS技术的DGMOSFET器件实现了用于阈值电压调整的自动自适应电路。仿真结果表明,该电路可以补偿静态和动态变化。这种采用DGMOSFET的自适应方法以及自适应电源电压缩放功能可根据特定应用的工作负载和要求,同时优化功率和性能。使用45 nm CMOS技术的仿真结果表明,这种自适应电路设计可以在相同能量下提供50%的更高性能,或者在相同性能下减少40%的能量。与仅采用动态电压缩放的常规方法相比,自适应调整阈值电压可降低功耗,同时保持其噪声容限。

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