Built in self test for ring addressed FIFOs with transparent latches

摘要

The use of special purpose complex embedded memories is becoming increasingly common. Their complex functionality, large sizes, decreasing feature sizes, and limited controllability/observability combine to make testing ever more difficult. In this paper, we describe a built in self test (BIST) method for testing ring addressed first in first out memories (FIFOs) that use transparent input latches for applications that require high data rates. The method used is compared to previous results for ring addressed FIFOs with edge triggered input latches. Several different special test modes are used to provide both more efficient and more complete BIST.