High speed robust current sense amplifier for nanoscale memories: a winner take all approach

摘要

The design of fast, low power and robust sense amplifier circuits is a challenge for nanoscale SRAMs due to the increasing bit line capacitance and process variations. Current sensing in SRAMs is promising to achieve high-speed operation in low-voltage application. In this paper, we propose a process variation tolerant, high performance and scalable current sense amplifier that uses a winner take all (WTA) approach for nanoscale SRAMs. Simulation of worst-case threshold voltage mismatch on our WTA sense amplifier shows that it could tolerate up to 10% variation in the threshold voltage, which is expected within die in a 70nm process. Detailed analysis of variation in the effective channel length (L/sub eff/) and supply voltage variation are also presented. A comparison of the sensing delay and energy consumption in 70nm technology shows that our WTA sense amplifier provides around 70-80% improvement in the sensing speed and consumes 28-70% less energy than the traditional voltage mode and current sense amplifiers.