Deterministic inter-core synchronization with periodically all-in-phase clocking for low-power multi-core SoCs

摘要

Periodically all-in-phase clocking (8-step frequency increments with a 4.5 ns switching time) and deterministic synchronous bus wrappers (synchronized data transfer among different frequency cores) are developed for dynamic voltage- and frequency-scaling multi-core SoCs. A maximum of 60% power reduction in MPEG-4 decoding with 1.5 to 2/spl times/ throughput increase are confirmed.