Self-timed circuitry for global clocking

摘要

We present an apparatus used to distribute a timing reference or clock across the extent of a digital system. Self-timed circuitry both generates and distributes a clock signal, while using less power and less skew compared to a clock tree. HSpice simulations, in a 180 nm CMOS process, comparing the distributed clock generator presented in this paper and an H-tree clock distribution system, each clocking a 16 mm/spl times/16 mm area suggests a 30% power savings. Also worst case skew was reduced from 27 ps to 2 ps while using a clock period equivalent to 9 FO4 gates.