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Degradation of Characteristics and Critical Bit-Flip Errors in Cascaded 3-Stage CMOS Inverters due to RF Interference

机译：级联3阶CMOS反相器中由于射频干扰而导致的特性下降和关键的位翻转误差

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《》|2005年|P.5-6|共2页
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Kyechong Kim; Iliadis; A.A.;
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专利

1. Operational upsets and critical new bit errors in CMOS digital inverters due to high power pulsed electromagnetic interference [J] . Kyechong Kim, Agis A. Iliadis Solid-State Electronics . 2010,第1期

机译：由于大功率脉冲电磁干扰，CMOS数字逆变器出现了操作失常和严重的新位错误
2. Critical Upsets of CMOS Inverters in Static Operation Due to High-Power Microwave Interference [J] . Kyechong Kim, Iliadis A.A. IEEE Transactions on Electromagnetic Compatibility . 2007,第4期

机译：由于大功率微波干扰，CMOS逆变器在静态操作中的严重故障
3. Degradation Characteristics of n- and p-Channel Polycrystalline-Silicon TFTs Under CMOS Inverter Operation [J] . Toyota Y., Matsumura M., Hatano M., Electron Devices, IEEE Transactions on . 2010,第2期

机译：CMOS反相器操作下n沟道和p沟道多晶硅TFT的降解特性
4. Degradation of Characteristics and Critical Bit-Flip Errors in Cascaded 3-Stage CMOS Inverters due to RF Interference [C] . Kyechong Kim, Iliadis A.A. International Semiconductor Device Research Symposium . 2005

机译：由于RF干扰，级联3级CMOS逆变器中的特性和临界位翻转误差的降解
5. Full Duplex CMOS Transceiver with On-Chip Self-Interference Cancelation [D] . Ayati, Seyyed Amir. 2017

机译：具有片上自干扰消除功能的全双工CMOS收发器
6. Fabrication of HfO2 patterns by laser interference nanolithography and selective dry etching for III-V CMOS application [O] . Marcos Benedicto, Beatriz Galiana, Jon M Molina-Aldareguia, 2011

机译：通过III-V CMOS应用激光干涉纳米光刻和选择性干法刻蚀制备HfO2图案
7. EXPERIMENTAL STUDY AND SPICE SIMULATION OF CMOS INVERTERS LATCH-UP EFFECTS DUE TO HIGH POWER MICROWAVE INTERFERENCE [O] . Haiyang Wang, Jiayin Li, Hao Li, 2008

机译：CMOS逆变器锁定效果的实验研究和Spice模拟由于高功率微波干扰
8. HYBRID SILICON-ON-SAPPHIRE/SCALED CMOS INTERFERENCE MITIGATION FRONT END BASED ON SIMULTANEOUS NOISE CANCELLATION, ACTIVE-INTERFERENCE CANCELLATION AND N-PATH-MIXER FILTERING. [R] . Krishnaswamy, H., Reiskarimian, N., Zhang, L. 2017

机译：基于同步噪声消除，主动干扰消除和N路径混合滤波的混合硅上蓝宝石/标定CmOs干扰减轻前端。

Degradation of Characteristics and Critical Bit-Flip Errors in Cascaded 3-Stage CMOS Inverters due to RF Interference

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