A PVT tolerant 0.18MHz to 600MHz self-calibrated digital PLL in 90nm CMOS process

摘要

This paper presents a digital PLL with logarithmic time digitizer, digitally-controlled oscillator, and start-up calibration, which achieves a constant damping factor and fractional loop bandwidth over a 0.18 MHz to 600 MHz range of output frequencies and PVT conditions, with output jitter less than 0.04 UIPP. The 0.18 mm/sup 2/ chip is implemented in 90 nm CMOS, operates over a 0.7 to 2.4 V power supply range and consumes 1.7 mW at 1 V and 520 MHz.