decision feedback equalisers; integrating circuits; CMOS analogue integrated circuits; radio receivers; decision feedback equalizer receiver; multidrop single-ended signaling systems; 2-tap DFE receiver; CMOS process; voltage margin; stubless channel; integrating receiver; ISI component; look-ahead receiver; interleaving receiver; sense-amp-based flip-flop; 2 Gbit/s;
机译:具有均衡VREF的DFE接收器,用于多点单端信令
机译:一个3.12 pJ /位,19-27 Gbps接收器,带有2抽头DFE嵌入式时钟和数据恢复
机译:具有2抽头DFE的5mW 6 Gb / s四分之一速率采样接收机,采用软判决
机译:用于多滴单端信令系统的2GB / s 2分接收器,具有降低的噪声
机译:非高斯噪声信号的接收器设计:在对称Alpha稳定和Middleton A类噪声模型中的应用
机译:在生物计算和生物传感应用中改善生物分子信号处理中的联网并降低噪声的流量系统设计
机译:一种用于浅水中预编码Oqpsk信号传输的盲多通道接收器