Clock skew (and jitter) is becoming the major obstacle to high-frequency clock distribution in sub-quarter micron CMOS LSIs, because skew cannot be scaled down even by use of scaled devices and may significantly increase as a result of device and operating environment deviations. To overcome this obstacle, the authors present skew-immune race-free impulse latch circuits and a reduced-skew ring-type clocking scheme. The 1 GHz clock test chip is integrated into a 6/spl times/6 mm/sup 2/ die with 0.18 /spl mu/m CMOS and double-layer-metal technology. The supply voltage is 1.8 V. The threshold voltage of the nMOS transistors is about 0.3 V and that of the pMOS transistors is about -0.3 V. 1 GHz global clock distribution shows less than 50 ps clock skew for those points on the chip.
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机译：时钟偏斜（和抖动）正成为四分之一微米CMOS LSI高频时钟分配的主要障碍，因为即使使用缩放设备也无法缩小偏斜，并且由于设备和操作环境的差异，偏斜可能会大大增加。为了克服这一障碍，作者提出了一种抗偏斜的无种族脉冲锁存电路和一种减小偏斜的环形时钟方案。 1 GHz时钟测试芯片通过0.18 / spl mu / m CMOS和双层金属技术集成到6 / spl次/ 6 mm / sup 2 /芯片中。电源电压为1.8V。nMOS晶体管的阈值电压约为0.3 V，pMOS晶体管的阈值电压约为-0.3V。1GHz全局时钟分布显示，芯片上这些点的时钟偏斜小于50 ps。
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