Channel engineering using B/sub 10/H/sub 14/ ion implantation for low Vth and high SCE immunity of buried-channel PMOSFETs in 4-Gbit DRAMs and beyond

摘要

Below the sub-0.25-/spl mu/m technology range, surface-channel (SC) PMOSFETs employing p+ poly-Si gates are widely used instead of buried-channel (BC) PMOSFETs employing n+ poly-Si gates. However, there are still many advantages of using an n+ poly-Si gate such as the absence of the undesirable Vth shift due to boron penetration through the gate oxide, no gate-dopant cross-diffusion, and process simplicity. The critical issues for extending the use of buried-channel PMOSFETs below the sub-0.25-/spl mu/m technology range, that is, the 4-Gbit DRAM era and beyond, are low Vth and also the suppression of short-channel effects (SCE), which can be achieved by an extremely shallow counter-doped layer with a high impurity concentration. Here, for the first time, we use decaborane (B/sub 10/H/sub 14/) ion implantation to fabricate a 20-nm-thick counter-doped layer and demonstrate an SCE-free high performance O.18-/spl mu/m BC-PMOSFET.