On the control-subroutine implementation of subprogram synthesis

摘要

The synthesis of VHDL procedures and functions is studied from the VHDL transformation point of view. Among all the proposed methods, inline expansion and modules can be integrated into a VHDL synthesis system by a source-to-source transformation, while a control-subroutine approach requires additional work at the higher-level synthesis phases before it can be linked to a logic synthesis tool. The possibility of carrying out a lot of optimization is explored during the process. We also present various generations of the control-subroutine approach, including the synthesis of recursive programs, a behavioral partitioning methodology that divides the controller into several communicating state machines, and a methodology that mixes the execution of subprograms. Our study shows that the combination of these approaches is flexible enough to be adapted to various applications in an efficient way.