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A timestamp-based selective invalidation scheme for multiprocessor cache coherence

机译:多处理器高速缓存一致性的基于时间戳的选择性失效方案

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Among all software cache coherence strategies, the ones that are based on the concept of timestamps show the greatest potential in terms of cache performance. The early timestamp methods suffer from high hardware overhead. Improvements have been proposed to reduce hardware overhead at the expense of either increasing runtime overhead or sacrificing cache performance. We discuss the limitations of the previous timestamp-based methods and propose a new software cache coherence scheme. Our scheme exploits the inter-level locality with significantly less hardware support than the early timestamp methods while introducing only constant runtime overhead for each epoch during the execution of a program. Simulation results show that the proposed scheme achieves higher performance than the previous schemes with comparable hardware overhead.
机译:在所有软件缓存一致性策略中,基于时间戳概念的策略在缓存性能方面显示出最大的潜力。早期的时间戳方法会承受较高的硬件开销。已经提出了以减少硬件开销为代价的改进,其代价是增加了运行时开销或牺牲了缓存性能。我们讨论了以前基于时间戳的方法的局限性,并提出了一种新的软件缓存一致性方案。与早期的时间戳方法相比,我们的方案利用层间局部性提供了更少的硬件支持,同时在程序执行期间仅为每个时期引入了恒定的运行时开销。仿真结果表明,该方案在硬件开销相当的情况下,比以前的方案具有更高的性能。

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