A new concept for accurate modeling of VLSI interconnections and its application for timing simulation

摘要

This paper presents a new concept for accurately modeling the timing behavior of VLSI interconnections using frequency domain methods and taking into consideration distributed parasitics as well as lumped elements and contact holes. A piecewise linear signal representation is used to catch the waveform dependencies of submicron structures. The models are applied in an analysis tool for clock trees and in a concept for accurate post-layout timing simulation.