A specification and validation method to improve concurrent systems reliability based on object messaging and rewriting logic

摘要

Design of real-time/concurrent systems requires formal approaches in order to facilitate verification and validation at each step. Methods based on formal logic have been previously suggested but they often work only in a specific domain and are generally only possible with specialized users. In an attempt to overcome these two restrictions, this paper proposes a method based on rewriting logic with user-friendly tools to increase software reliability. Different tools are proposed to support this approach: a graphical editor for the specification of the structure and the behaviour of objects, a prototype generator, and an inference engine for rule validation based on rewriting logic decidability.