首页> 外国专利> METHOD AND DEVICE FOR SEPARATELY EVALUATING LOGIC CIRCUIT, METHOD AND DEVICE FOR PREPARING PRODUCT SPECIFICATION DATA BASE, METHOD AND DEVICE FOR ESTIMATING PRODUCT SPECIFICATION AND METHOD AND DEVICE FOR AUTOMATICALLY GENERATING LOGIC CIRCUIT HIERARCHY

METHOD AND DEVICE FOR SEPARATELY EVALUATING LOGIC CIRCUIT, METHOD AND DEVICE FOR PREPARING PRODUCT SPECIFICATION DATA BASE, METHOD AND DEVICE FOR ESTIMATING PRODUCT SPECIFICATION AND METHOD AND DEVICE FOR AUTOMATICALLY GENERATING LOGIC CIRCUIT HIERARCHY

机译:分别评估逻辑电路的方法和设备,准备产品规格数据库的方法和设备,用于评估产品规格的方法和设备以及用于自动生成逻辑电路层次结构的方法和设备

摘要

PURPOSE: To provide the method for calculating a classified value showing the feature of wiring relation from the geometrical relation of logic circuits. ;CONSTITUTION: In a step 10, logic elements provided for the logic circuits and the wiring relation are inputted to an electronic computer. In a step 20, a first-order adjacent logic element number N1 is calculated from the inputted logic elements and wiring relation as the total number of first-order adjacent logic elements directly connected with all the respective logic elements provided for the logic circuits. In a step 30, an in-second-order adjacent logic element number N2 is calculated from the inputted logic elements and wiring relation as the total number of the total number of first-order adjacent logic elements and the total number of second-order adjacent logic elements directly connected with the respective first-order adjacent logic elements. In a step 50, difference between the logarithmical value of the first-order adjacent logic element number N1 and the logarithmical value of the in-second-order adjacent logic element number N2 is extracted as a classified value λ for the features of logic circuits.;COPYRIGHT: (C)1994,JPO&Japio
机译:目的:提供一种从逻辑电路的几何关系中计算出表示接线关系特征的分类值的方法。组成:在步骤10中,将为逻辑电路和接线关系提供的逻辑元件输入到电子计算机。在步骤20中,根据所输入的逻辑元件和布线关系,将一阶相邻逻辑元件数量N1计算为直接与为逻辑电路提供的所有各个逻辑元件直接连接的一阶相邻逻辑元件的总数。在步骤30中,从输入的逻辑元件和布线关系中计算出二阶相邻逻辑元件数N2,作为一阶相邻逻辑元件总数和二阶相邻逻辑元件总数的总和。逻辑元件直接与相应的一阶相邻逻辑元件连接。在步骤50中,针对逻辑电路的特征,将一阶相邻逻辑元件编号N1的对数值与二阶相邻逻辑元件编号N2的对数值之间的差提取为分类值λ。 ;版权:(C)1994,JPO&Japio

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