A comparative study of single-phase clocked latches using estimation criteria

摘要

The advantage of using single-phase clocked circuits in VLSI system design is well known. This class of circuits has the advantage of simple clock distribution, low area for clock routing, reduced clock skew, and high speed. However, it is difficult to compare the characteristics and performance of these circuits, because there are no clear evaluation criteria. Indeed, such criteria are related to the application context and may therefore be misleading when taken out of context. In this paper, we will present a set of criteria which will permit designers to choose the most appropriate circuit in a particular case and therefore, obtain useful results. The proposed criteria will reduce the simulation time and help designers to reach better solutions in less design time.