An algorithmic analog-to-digital converter with low ratio- and gain-sensitivities 4N-clock conversion cycle

摘要

This paper describes a new SC method to reduce the capacitor mismatching error and finite-gain error in an ADC. Through the use of switched-capacitor techniques, the proposed new ADC is insensitive to the capacitor-ratio accuracy as well as the finite gain and the offset voltage of the operational amplifiers. The switching error becomes the only major error source. Moreover, the cycle time for n-bit conversion is reduced to 4n-clock time. Both SWITCAP and HSpice simulations have been performed to verify the performance of the new ADC. It is shown that a 15-bit resolution at the sampling frequency of 20 KHz can be achieved when the capacitor ratios have a variation of 1% and the finite gain of the op amps is only 65 dB.