Testable programmable digital clock pulse control elements

摘要

Digital clock pulse control elements - delay lines and pulse-shaping elements - are used widely for clock generation and clock tuning in synchronous digital logic. However, they are intrinsically redundant circuits: without special modifications, DC logic testing cannot completely verify their static behavior (including the correct operation of the decoders and selectors used for their programming and control). This paper demonstrates low overhead circuit modification techniques that can be applied to all classes of programmable clock control elements, ensuring their complete single stuck-at fault testability.