Extension of TISSS test methodology from chip level to board level for improved transportability and decreased life-cycle costs

摘要

This paper discusses an implementation of a set of tools designed to improve the supportability and transportability of board level Test Program Sets (TPSs) to multiple test environments. The Tester Independent Support Software System (TISSS) was tried and proven sufficient to test advanced tactical fighter (ATF) complex digital line replaceable modules (LRM). The proposed methodology is an extension of the TISSS philosophy for component level testing in which computer aided design (CAD) designer data is extracted, formatted into generic Institute of Electrical and Electronic Engineers (IEEE) standard formats, translated and postprocessed into tester specific TPSs. This new TPS re-host method will use tools derived from TISSS, Commercial-Off-The-Shelf (COTS) packages, and will be supplemented by some Rome Laboratory customized software tools. The aim of this effort is to demonstrate to the depot maintenance repair community a better approach to TPS development and re-hosting versus conventional methods in terms of reduced costs, time and improved efficiency.