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Block-diagram-level design capture, functional simulation, and layout assembly of analog CMOS ICs

机译：模拟CMOS IC的方框图级设计捕获，功能仿真和布局组装

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《》|1993年|P.2090-2093|共4页
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Current; K.W.; Parker; J.;
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中图分类无线电电子学、电信技术;
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专利

1. Cell libraries and assembly tools for analog/digital CMOS and BiCMOS application-specific integrated circuit design [J] . Smith M.J.S., Portmann C., Anagnostopoulos C., IEEE Journal of Solid-State Circuits . 1989,第5期

机译：用于模拟/数字CMOS和BiCMOS专用集成电路设计的单元库和组装工具
2. Cell Libraries And Assembly Tools For Analog/digital CMOS And BiCMOS Application-specific Integrated Circuit Design [J] . Smith M.J.S., Portmann C. IEEE Journal of Solid-State Circuits . 1989,第5期

机译：用于模拟/数字CMOS和BiCMOS专用集成电路设计的单元库和组装工具
3. Strategic Learning of Simulation and Functional Analysis in the Design and Assembly of Mechanisms With CAD on a Professional Master's Degree Course [J] . BASILIO RAMOS BARBERO, RAFAEL GARCIA GARCIA Computer applications in engineering education . 2011,第1期

机译：专业硕士学位课程中用CAD设计和组装机构的仿真和功能分析的战略学习
4. Block-diagram-level design capture, functional simulation, and layout assembly of analog CMOS ICs [C] . Current K.W., Parker J., Institute of Electric and Electronic Engineer International symposium on circuits and systems . 1993

机译：模拟CMOS IC的框图级设计捕获，功能模拟和布局组装
5. Bipolar device characterization and design in CMOS technologies for the design of high-performance low-cost BiCMOS analog integrated circuits [D] . Larsen, Frode. 1994

机译：CMOS技术中的双极性器件表征和设计，用于设计高性能低成本BiCMOS模拟集成电路
6. Simulations and Design of a Single-Photon CMOS Imaging Pixel Using Multiple Non-Destructive Signal Sampling [O] . Konstantin D. Stefanov, Martin J. Prest, Mark Downing, 2020

机译：使用多个无损信号采样的单光子CMOS成像像素的仿真和设计
7. Peer Review: Layout Design and Simulation Analog Neural Network Circuit Using Cmos Technology 0.35 Micron [O] . Kurniawan Robby, Heruseto Brahmantyo, Prasetyo Eri, 2016

机译：同行评审：使用Cmos技术0.35微米的布局设计和模拟模拟神经网络电路
8. Optimal Layout of CMOS Functional Arrays. [R] . Uehara, T., vanCleemput, W. M. 1978

机译：CmOs功能阵列的最佳布局。

Block-diagram-level design capture, functional simulation, and layout assembly of analog CMOS ICs

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