An architecture with low memory-bandwidth and less hardware cost for 3SBM algorithm

摘要

The 3-step block matching (3SBM) algorithm has become one of the basic techniques in the area of motion estimation. The paper presents a pipeline architecture to perform this algorithm in real time. The major advantages of the architecture are (1) only two image memory modules are needed, (2) this architecture has less hardware cost and is suitable for VLSI implementation, (3) this architecture can be used in HDTV application.