A real-time reconfiguration algorithm for fault-tolerant VLSI and WSI arrays

摘要

Reliability is an important issue in the real-time operations of VLSI array processors. A new algorithm for the real-time reconfiguration of VLSI and WSI arrays is presented. This algorithm is characterized by its simplicity and locality. The control of this reconfiguration scheme is implemented in hardware for a real time execution. It supports multiple faults including transient/intermittent faults with a zero degradation time. Simulation results show that a good spare utilization rate is achieved with a computational complexity that is independent of the array size.