The use of an additional metal layer on a large CMOS ASIC part provides a practical method for converting an existing chip design with wirebond or tape automated bonding (TAB) peripheral pads to an array of flip chip solder bumps across the chip surface. While there are advantages to single chip packages with flip chip interconnect, multichip modules are required to take full advantage of flip chip packing density and performance gains. Compared with single chip packages on a printed circuit board, flip chip multichip modules offer about a 10* surface area reduction. Propagation delays in signal interconnect lines are about three times faster for the module than single chip packages on a printed circuit board.
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