Multilevel dynamic storage employing refreshing schemes potentially allows very compact synapses with fast read and write operations. A circuit implementation is described which performs an 8-b to 10-b transmission of dynamically stored value and a 2-MHz, successive approximation, A/D to D/A (analog-to-digital to digital-to-analog) conversion. The synapse size is 105 mu m*75 mu m for a 2- mu m process. This implementation is capable of bandwidths in the low megahertz (1 to 20 MHz).
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