EURO-DAC '92. European Design Automation Conference, EURO-VHDL '92 (Cat. No.92CH3126-0)

摘要

The following topics are dealt with: asynchronous design techniques; timing issues in high-level synthesis; application of formal methods; architectural synthesis; timing analysis and verification; module generation; combinational logic synthesis; systems engineering and mechatronics; top-down physical design; finite state machine design; topological optimization in routing; design for testability; fault simulation; VHDL-related models; VHDL standardization; and formal verification in VHDL.