A VLSI array architecture for the on-line training of recurrent neural networks

摘要

The authors show how to derive systematically a VLSI systolic array for the real time recurrent learning (RTRL) algorithm of D. Zipser and R.J. Williams (1989). The main goal is to match the RTRL algorithm to the ring architecture proposed by J.N. Hwang et al. (1990) that was shown to be generally applicable to many neural network models. Although this task was a straightforward extension for the retrieving phase, skillful reformulation of the learning phase was necessary. The control complexity and memory requirements of the processing elements remain reasonably low.