A second-generation reduced-instruction-set-computer (RISC) architecture designed to support superscalar implementations which can execute multiple instructions every cycle is described. The architecture provides compound-function instructions that allow application path lengths to be less than would be required on many complex-instruction-set computers. This new RISC architecture also exploits advances in optimizing compiler and operating system technology. The processor architecture is based on a logical view of the processor consisting of three independent functional units: a branch processor, a fixed-point processor, and a floating-point processor. The key feature of these functional units is that they are designed for maximum concurrency among the units.
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