Ada on reduced instruction set computers, for real-time embedded systems

摘要

The 32-bit reduced-instruction-set-computer (RISC)-based processors have been identified by the Joint Integrated Avionics Working Group as a potential successor to the MIL-STD-1750A 16-bit processor for military applications. It is pointed out that there are a number of important performance issues associated with using high-order languages such as Ada on RISC-based systems. These issues include code generation, register allocation, and pipeline performance. These issues need to be properly addressed when selecting a processor/compiler pair for a project. It is noted that special benchmarks developed to evaluate individual Ada construct performance can be used not only for compiler and processor evaluation and selection, but also to create guidelines that provide timing and size quantization directed at identifying the most efficient set of Ada constructs. Available benchmarks, such as the Common Ada Missile Packages (CAMP) Armonics benchmarks, should be used to provide application-specific criteria for processor-compiler pairs.