A description is given of the ways in which the environment of a highly parallel, high-latency interconnection network is different from that encountered in a uniprocessor system. The impact of these differences on the design of the processing elements is discussed. Methods that can be used to evaluate the impact of architectural choices on the performance of any system that uses a similar network are examined. Two detailed designs of processing elements, one using a CISC (complex-instruction-set computer) processor and the other using a RISC (reduced-instruction-set computer) are given as examples.
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