A set of 1.5- mu m (0.9- mu m effective channel length) CMOS integrated circuits has been designed, fabricated, and tested which perform real-time 20-MHz digital signal processing (DSP). The set includes an 8-bit, 64-tap transversal filter (MFIR); a 1-bit, 1024-tap transversal filter and template matcher (BFIR); a 12-bit, 64-tap rank-value filter (RVF); and an 8-line 512-pixel variable-length video shift register (VSR). The chip set is fully functional and operates at 20 MHz. All components in the family can be used together or in a stand-alone fashion. To enhance the flexibility of the processors, each has a reconfigurable window to allow both one-dimensional and two-dimensional processing. The window size and/or the data and coefficient precision of the two transversal filters can be increased by using multiple processors without the need for external components.
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