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SH 100E 10000 gate ECL/15000 gate CML gate array family with ECL/TTL I/O compatibility

机译:具有ECL / TTL I / O兼容性的SH 100E 10000门ECL / 15000门CML门阵列系列

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摘要

A novel bipolar gate array family is described. The family consists of four arrays and two macro libraries. With ECL (emitter-coupled logic), complexity ranges from 1500 to 10 000 equivalent gates, and with CML (current-mode logic), complexity covers 2250 to 15000 equivalent gates. Both CML and ECL macros can be mixed on any customer-defined chip. This novel duality allows tradeoffs between performance, power, and complexity on the same chip. The I/Os are designed to serve both ECL and TTL interfaces.
机译:描述了一种新颖的双极门阵列家族。该系列由四个阵列和两个宏库组成。使用ECL(发射极耦合逻辑)时,复杂度范围为1500至10000个等效门,而使用CML(电流模式逻辑)时,复杂度则覆盖2250至15000个等效门。 CML和ECL宏都可以在任何客户定义的芯片上混合使用。这种新颖的双重性允许在同一芯片上的性能,功耗和复杂性之间进行权衡。这些I / O旨在服务于ECL和TTL接口。

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