A methodology for first time correct gate array designs

摘要

Application Specific Integrated Circuits (ASICs) can bring many benefits. There are however, some actual and perceived risks in using this 'new' technology. In order to maximize the benefits of the technology, an ASIC design methodology must be developed which takes into account differences between traditional PCB type development and ASICs. This paper explores a suitable methodology, which has been validated on a number of designs. The differences between traditional PCB type developments and the design of ASICs is used as a basis for evolving a suitable methodology.