On Some Architectural Issues of Optical Hierarchical Ring Networks for Shared-Memory Multiprocessors

摘要

Optical hierarchical ring networks with 2 and 3 levels for multiprocessors are studied through simple analytical modeling and extensive simulations. The performance of the four possible deflection routing schemes to resolve contentions is simulated and found to be relatively the same. Comparison of deflection routing and buffering, under the assumption that each slot contains one bit along the temporal dimension, shows that the transaction delays in systems using deflection routing increase faster than in systems with buffering with an increase in traffic intensity. However, the performance gain by reconfiguring from a 2-level deflection system to a 3-level system is significant, and the gain can outperform buffering in a 2-level system. It is postulated, nevertheless, that deflection routing should outperform the buffering scheme when each slot contains more bits along the temporal dimension, because the o-e and e-o cost of the latter is proportional to the number of bits whereas it is constant for the former. Non-contention optimal configurations are found by minimizing the maximum transaction delay and the average transaction delay. However, when contentions are considered, those configurations that minimize the average non-contention delay perform worse than those which minimize the maximum non-contention delay. The poor performance is the result of quick saturation at the global ring. However, configurations that result from minimizing the maximum or average non-contention delay may be far from the true optimal configuration specific to a particular workload, especially when the traffic load is high, and traffic is localized.