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Innovative Application of a Passive Device Failure Analysis Technique to a JFET

机译:无源器件故障分析技术在JFET上的创新应用

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摘要

A technique normally used for the analysis of tantalum capacitor failures was successfully applied to a JFET. The JFET had a short from the source to the gate. The short was located at the source bond pad and had resulted from a combination of the use of too large a bond wire and excessive bnding pressure. The exact location of the site of the short was successfully determined by using a copper electroplating technique typically used for locating shorts or leakage sites on the tantalum slug of a tantalum capacitor.
机译:通常用于分析钽电容器故障的技术已成功应用于JFET。 JFET从源极到栅极短。短路位于源极焊点处,是由于使用太大的焊线和过高的焊接压力共同导致的。通过使用通常用于在钽电容器的钽芯上定位短路或漏电部位的铜电镀技术,成功确定了短路部位的确切位置。

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