A 9.2b 47fJ/conversion-step asynchronous SAR ADC with input range prediction DAC switching

摘要

This paper presents a 10b 500KS/s asynchronous successive approximation register analog-to-digital converter (SAR ADC) with input range prediction DAC switching technique for low power applications. The proposed input range prediction DAC switching technique narrows down the traditional try-and-error range of the input signal to prevent unnecessary DAC switching, and the average switching energy is 90% more efficient than the conventional approach. A prototype is fabricated in 0.18um CMOS technology. With a single supply of 1V, it achieves an ENOB, SNDR and FoM of 9.24b, 57.3dB, and 47fJ/Conversion-step at 500KS/s sampling rate, respectively.