Modeling discrete event system with distributions using SystemVerilog

摘要

Discrete event systems (DES) are a type of dynamic system in which the system behaviour is governed by discrete events occurring asynchronously over time. Most of the logical controllers used now are examples of DES. In this paper we describe the problem faced while modeling a queuing system (which is an example of DES) using constraints in SystemVerilog. The method to overcome the problem is explained and a retrial queuing system is modeled using SystemVerilog. The advantages of modeling DES in SystemVerilog are explained. The performance analysis is done on the SystemVerilog model, compared with another language model called MOSEL.