Performance Analysis of SoC Communication by Application of Deterministic and Stochastic Petri Nets

摘要

Design space exploration (DSE) for heterogeneous Systems on Chip (SoCs) is a key issue as today's SoC complexity is steadily increasing. Methods for the estimation of implementation specific performance and cost features on all levels of design have to be developed. This contribution proposes an approach utilizing deterministic and stochastic Petri nets (DSPN) to analyze on-chip communication which is of increasing importance. In order to demonstrate the suitability of this approach the on-chip communication structure of two examples featuring typical SoC communication conflicts like competition for common communication resources have been studied. A modem heterogeneous DSP and a design example with an on-chip bus have been examined. The results show that sufficient modeling accuracy can be achieved with low modeling effort in terms of computation and implementation time.